By reading a video signal recorded in a recording medium such as a video disk, then writing it as a digital signal in a memory, followed by starting to read that stored signal with a timing which has a prescribed time difference from the start timing, there is, obtained a video signal that has a signal read from the recording medium. In addition, it is possible to give a special processing such as reduction, amplification or the like to the signal by controlling the address at the time of reading it from the memory. A signal regeneration processor which executes regeneration and processing of a video signal based on such knowledge has already been disclosed.
On the other hand, in regenerated signals obtained from the recording medium there may be generated missed portions of the signals, the so-called dropout, due to flaws in the recording medium, adherence of dirt on it or the like. In addition, it is known that in a regenerated signal there often exists a time axis error due to uneven rotation or the like of the disk or the like. Accordingly, it is indispensable in a signal regeneration processor to provide for means to correct the dropout, the time axis error and the like. Such a signal regeneration processor is shown in FIG. 8.
In FIG. 8, video signal a which is an output from a playback unit 1 such as a video disk player is supplied to an A/D (analog to digital) conversion circuit 2. Further, in the playback unit 1 there is incorporated, for example, a dropout detection circuit which outputs a dropout detection signal b that indicates the occurrence of a dropout when the interval between the zero-crossing points of RF signals read from the recording medium exceeds a predetermined value.
In the A/D conversion circuit 2, a video signal is sampled and the obtained sample value is converted to a corresponding n-bit digital data by quantizing it. The video data output from the A/D conversion circuit 2 is supplied to a dropout code replacement circuit 3. To the dropout code replacement circuit 3 there is supplied a dropout detection signal b from the playback unit 1, and the dropout code replacement circuit 3 replaces the video data during the dropout period with a dropout code consisting, for example, of the upper limit code for the n-bit digital code by means of the dropout detection signal b.
A video data output from the dropout code replacement circuit 3 is supplied to a field memory 4. The field memory 4 possesses a storage capacity which can store n-bit video data output during one field period. Further, a write and read address signal and a write and read control signal are supplied to the field memory 4 from a memory control circuit 5.
Data read from the field memory 4 is supplied to a line memory 6, a changeover switch 7 and a dropout code detection circuit 8. The line memory 6 consists of FIFO (first in and first out) memory having a storage capacity sufficient to store data obtained during one horizontal scanning period (referred to as 1H hereinafter). Data read from the field memory 4 by the line memory 6 is delayed by 1H and is supplied to one of the input terminals of the changeover switch 7. To the other input terminal of the changeover switch 7 there is directly supplied data read from the field memory 4. In addition to the controlled input terminal of the changeover switch 7 there is supplied the output of the dropout code detection circuit 8 as the changeover command signal. The changeover switch 7 is constructed so that it selectively outputs data read from the memory 6 in the presence of a changeover command signal, and selectively outputs data read from the memory 4 in the absence of a changeover command signal. Further the dropout code detection circuit 8 is arranged to output a detection signal when there exists a dropout code in a data read from the field memory 4. Consequently, video data output from the changeover switch 7 is replaced by the video data at the time earlier than that time when there occurs a dropout, in order to correct the dropout. The output data of the changeover switch 7 is supplied to a D/A conversion circuit 9 where it is converted to an analog signal to become a video signal.
As described above, in the prior art signal regeneration processor there is needed a line memory on the reading side of the field memory. The line memory is required to operate at a high speed, and is very expensive, and it is difficult to improve the actual efficiency because of its high consumption of power. For these reasons, the prior art device has a drawback in that its manufacturing costs are high and that it is difficult to realize a reduction in power consumption and rendering the device small in size.